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I'd love to see: (1) some analysis of the usefulness of these extra instructions, perhaps compared to Intel's MMX instructions and their subsequent SSE instructions in the Pentium 3, or even compared to AltiVec, and (2) some analysis of whether the 3DNow! instructions were actually used by developers. I recall the suspicion was that 3DNow! was all hype and marketing. Tempshill 22:07, 1 Mar 2004 (UTC)

As far as I know Microsoft DirectX and mplayer heavily use 3DNow! when available. But since virtually all x86 processors now support SSE the interest in 3DNow! generally fades away.Zuxy

It says "However, 3DNow! instructions can generally be executed with a lower latency and throughput than SSE instructions." Does this mean lower latency AND lower throughput? This is unclear, especially as the contexts seem to present an advantage over SSE.

latency means how long it takes to perform 1 instruction; throughput means how long it takes to perform each subsequent instruction. so lower latency and lower throughput = quicker execution

Rumour or truth

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Long time ago I've heard that when a program simply used MMX or x87 instructions, the processor is able to real-time change the code to use better and faster 3DNow! instructions without any application intervention or modification.

Is that real, or was only a rumour?

—Claunia 23:17, 27 August 2005 (UTC)[reply]

It's a rumor, I'm afraid. Recent x86 processors (newer than Pentium Pro and K6) translate x86 instructions into RISC-like micro-ops on the fly and schedule/execute these micro-ops, but there's no x87->3DNow! translation. Programs have to rewritten and recompiled to use 3DNow! instructions.Zuxy

3dnow2?

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I was running mplayer to watch a video on my linux ststem, and saw the following among its output MPlayer dev-SVN-rUNKNOWN-4.1.2 (C) 2000-2007 MPlayer Team
CPU: AMD Athlon(tm) 64 Processor 3200+ (Family: 15, Model: 12, Stepping: 0)
3DNowExt supported but disabled
CPUflags: MMX: 1 MMX2: 1 3DNow: 1 3DNow2: 0 SSE: 1 SSE2: 1

Does anyone know anything about this 3DNow2 flag? --Pandora Xero 13:49, 5 September 2007 (UTC)[reply]

Drop the exclamation mark?

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Should we? It does look a bit silly that every time 3DNow! is mentioned we have !!!!! Rilak (talk) 11:16, 20 March 2009 (UTC)[reply]

It's part of the trademark, so it has to stay. Compare with the Yahoo! article. C xong (talk) 02:42, 4 March 2010 (UTC)[reply]

Remove the word rape?

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I don't think that the first sentence should contain the word rape. TheWaters (talk) 23:56, 1 September 2009 (UTC)[reply]

Can be wrong assumption

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From article: "Software written to use AMD's 3DNow! instead of the slower x87 FPU could execute up to 4x faster, depending on the instruction-mix."

It can be not true, just assuming, that x87 FPU is 80 bits, and "3Dnow!" is 128 bits, and that if you use 4 single precision (four 32 bit), then it fit into 128bit (32*4). But there is highly possibility that "3Dnow!" (as well as SSE instructions) are based on calculation of earlier instructions (on general purpose instructions in CPU as "x87 FPU" instructions as well). So this instructions just simplify programing and do not making calculation any faster at all. For example code written in C++ of cosine function and code of SSE instruction of cosine function will be calculated in same time don't matter it is for scalars or vector.xyzw. Only if you somehow really can prove that begining with "x87 FPU" instructions (which are since 486 CPU) there was added additional 80 multiplication and similar calculations (-,+,/) units. But even general purpose instructions (at least in modern processors) are 32 bits or 64 bits (16 bits for 8086/286 and 32 for 386DX and till Pentium 4 and then goes 32bits and 64bits for "Core i7" and 64bit types CPU's). My guess is that there is only one unit of multiplication, subtraction, addition and division (and those are in general purpose instructions since 8086). All over SSE based on those, so are just concurrency of where to hold instructions in CPU some kind BIOS (or ROM) or in C++ codes (HDD). And I mean there no any clue to understand how much faster, for example, calculation of 4 cosine numbers parallel using SSE instructions, than calculating cosine using your Taylor series code, which would not use neither SSE nor "3Dnow!" nor any over (except maybe those which are since 8086 or 386 CPU). I think it should be 4 cosine SSE parallel still slower four times than one cosine (using Taylor series) based on 8086 instructions (GP). — Preceding unsigned comment added by Versatranitsonlywaytofly (talk • contribs) 13:40, 26 February 2012 (UTC)[reply]
I mean on free pascal there 16 decimal (64 bits) number addition operation done in 1/16 of clock, so with 3GHz you can done 3000/16=187.5 addition operations or about the same amount multiplication operations. So If there would be such thing as four 32 bit (8 decimal digits = 32 bits) floating point scalars additions or multiplications in one cycle, then there wouldn't be needed 3D graphics accelerators. My suggestion is that 287 and 387 and 8087 chips are not coprocessors, but instructions ROM's (like only readable nand flash memory on SD 16 GB memory card).

PrefetchW

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I was directed here by the Broadwell article that says the Broadwell processor will support prefetchw. Any info on this here? — Preceding unsigned comment added by 38.97.97.99 (talk) 18:45, 17 April 2014 (UTC)[reply]

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These external links do not link to a specific page: 2 - AMD 3DNow Instruction Porting Guide (PDF) 3 - 3DNow Technology Manual 4 - AMD Extensions to the 3DNow and MMX Instruction Sets Manual 6 - AMD Geode LX Processors Data Book — Preceding unsigned comment added by Cor Koomen (talk • contribs) 13:24, 13 August 2014 (UTC)[reply]

Hello there! Have you tried to rescue them using the Wayback Machine? — Dsimic (talk | contribs) 03:29, 16 August 2014 (UTC)[reply]
Hi, thanks for the comment. I just tried. Do you think this will do for the fifth external link? new link. — Cor Koomen (talk) 10:40, 17 August 2014 (UTC)[reply]
Unfortunately, Wayback Machine doesn't have that page archived. — Dsimic (talk | contribs) 08:48, 20 August 2014 (UTC)[reply]
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